Archive June 2026

We are currently evaluating NXP’s i.MXRT1062 CPU based MCUs as the core of our PMU-001 device.

This product is advantageous as it one of the most capable MCU in terms of raw processing power, while also featuring a FPU.

Additionally, the presence of an Ethernet module with IEEE1588 ptp functionality, gives access to an adjustable free running nanoseconds timer counter with 1 sec rollover. A robust hardware on the fly correction capability allows disciplining the counter using a pps GPS signal or an ethernet based LAN ptp clock.

Note that the additional processing power has the effect of reducing IRQ contention which may introduce jitter. Faster CPU also means availability of larger PLL scales. the cycle counter has a resolution of 1/600 Mhz, while the IEEE1588 counter timer has a resolution of 40ns

As for disciplined sampling periods, the periodic interrupt timer (PIT) period can be precisely controlled with a period correction resolution of either 1/24 Mhz or 1/150 Mhz, depending on the clock source, using the LDVAL register that affects the next period, not the current period, ensuring consistent sampling.

A simple integer accumulator and integer divider method allows distribution of corrections smaller than one period correction resolution, ensuring total correction over one second brings the IEEE1588 timestamping to a disciplined second, as well as the PIT correction that ensures a true sample rate of electrical data close to nominal.

Following is the jitter analysis at 27C temperature ambient, CPU at 56C, and a 60 second recording interval of USB sample and timestamp data. No frame drops observed. The jitter analysis was performed during nominal GNSS function (no holdover).

Nominal sampling rate is 50 ksps (20 us). 8 channels recorded, 7 samples per frame, frame rate : 140 us.

symlog/log scale

As for the MCU discipline protocol : Periodic IEEE1588 timestamp timer discipline is performed every 20us sampling period, PIT timer discipline (LDVAL nominal ticks + correction) is also performed every 20us. The method used for determining the correction factor is : proportional term representing the CPU cycles phase error (absolute, not fractional error) over each pps interval, summed with an infinite integral of the residual IEEE1588 counter phase error (absolute, not fractional), also over each pps interval. Filtering of the CPU cycles phase error outliers was done by filtering out measurements above 4 sigma. The sample population maintained for average,mean and standard deviation calculations are the last 64 CPU cycles phase errors recorded (so, an history of 64 seconds)

Allan Deviation chart

This is the Allan deviation calculation of the free-running CPU cycles counter, normalized to nanoseconds, and the IEEE1588 disciplined nanoseconds counter, over 41785 seconds, with a unit measurement interval tau of 1 second, while performing sampling of electrical parameters nominally at 50000 samples par second, 8 channels sampled, 7 samples * 8 channels per USB frame, and sending data over USB, but without a host listening.

We plan to perform the same measurements and Allan deviation charts without the payload calculation.
Results are deemed quite satisfactory, and follow expected noise characteristics and temperature drift effects. Average temperature 45.70C @CPU, with forced convection in front of the XTAL, with CPU downstream, Average ambient temperature 25C, measurement performed at night starting at 21:30 UTC. Environment temperature is not controlled.

I will provide an updated chart with temperature data soon.

Temperature compensation

We are also evaluating an additional high precision temperature probe positioned right under the XTAL to provide ppm correction during GPS holdover intervals, with an intended goal of < 1ppm deviation during GPS holdover intervals. Such a fixture, besides providing TCXO capability without the need of replacing the onboard XTAL, also improve robustness of GPS pps signal outlier filtering, by providing ppm deviation prediction based on temperature slew, provided the temperature measurement is itself low noise. This would help identify the very infrequent but possible GPS pps glitches.

Such level of discipline precision is adequate a field microPMU, which is our intended market segment,

Discarding the requirement for an external OCXO or TCXO driven MCU or sampling timer would drastically lower R&D production, and time to market delays.

At this point in time AD7606 interfacing has been done on the new MCU platform with satisfying results.

Thus, We are now moving our development efforts towards PCB design.

For more information about i.MX-RT1060 and i.MX-RT1062 based MCUs :

https://www.nxp.com/products/i.MX-RT1060

https://www.pjrc.com/store/teensy41.html

Rework and Refactoring of the Host based PMU logic

We are currently in the process of updating our host based code to improve overall performance and add a substantial margin of processing time taking into account all PMU P-class and M-class modes and reporting rates, So as to deliver a product that is adequate to a large segment of cost effective and available SoC platforms, and ensuring device form factor compliance for size restricted cabinets and challenging thermal environments. This should not alter significantly the mentioned December 2026 deadline for a commercially adequate product delivery.

Stay tuned !